1. Field of the Invention
The present invention relates to a multi-cycle path analyzing method for detecting a multi-cycle path which can take 2 cycles or more for a signal to propagate from the starting point of the path to its end point, for example, among paths between two memory elements within a circuit to be analyzed in a timing analysis and logic verification of a digital circuit.
2. Description of the Related Art
A multi-cycle path in a digital circuit is a path that can take time of two cycles or more for a signal propagate from a memory element at a starting point to that at an end point, for example, between the two memory elements. Generally, a path between memory elements is handled as a single cycle path on which a signal propagates in one cycle.
If a delay between the memory elements becomes large, a design becomes difficult when the path between the memory elements is handled as a single cycle path. By detecting a multi-cycle path which may take two cycles or more from the starting point of the path to its end point, restrictions are eased to be able to facilitate a design.
Conventionally, not many techniques that are effective for a multi-cycle path analysis exist, and normally, a human being specifies a multi-cycle path at the time of design.
The following document exists as a conventional technique in the case where a pure logic circuit is targeted.
H. Higuchi: An Implication-based Method to Detect Multi-Cycle Paths in Large Sequential Circuits, IEEE/ACM Design Automation Conf. pp. 164–169, 2002
However, in an actual normal digital circuit, logic gates are mapped by cells of a cell library. Therefore, two clocks or more exist, and a gated clock is used. Accordingly, it has been difficult to automatically detect a multi-cycle path in an actual digital circuit.
Additionally, there has been a method calculating the state transition of a circuit, namely, reachability from the initial state by recognizing the entire circuit as one finite state machine, and using the reachability so as to detect a multi-cycle path. This method is described by the following document.
K. Nakamura, et al., “Waiting False Path Analysis of Sequential Logic Circuits for Performance Optimization”, IEEE/ACM ICCAD 98, pp. 392–395
However, since an entire circuit is handled as one finite state machine with this method, the scale of a finite state machine becomes enormous if the circuit becomes complex. Therefore, this method is not always effective as a practical method for detecting a multi-cycle path.
Furthermore, with a conventional method detecting a multi-cycle path by altogether recognizing paths between two memory elements, it cannot be determined whether or not a targeted multi-cycle path is actually activated, namely, whether or not a change in the value of a memory element at a starting point propagates to a memory element at an end point over the path, or whether or not a change in the value of a memory element at a point other than the starting point propagates to the memory element at the end point.
With an increase in the scale of a circuit in recent years, a multi-cycle path analysis has become complex, and-its processing time has become large. Besides, if a clock is complex such as in the case where a gated clock is used, an influence of the clock cannot be accurately determined, and there are difficulties in the detection of a multi-cycle path.
Additionally, with a conventional method detecting a multi-cycle path by altogether recognizing paths between two memory elements, it is not examined whether or not a targeted multi-cycle path is actually activated. Therefore, an ability to detect a multi-cycle path is degraded.
Furthermore, if a multi-cycle path is specified by a designer at an early stage of design, the specification of the multi-cycle path is normally fixed, and a path the timing of which is strict is not actually specified at a stage after the design. As a result, a timing restriction is not satisfied. Besides, variations in a circuit delay in chip manufacturing tend to increase. However, since a timing restriction is fixed at the time of design, a product yield is degraded.